Do you have a passion working on leading edge technology? Are you passionate about working closely with next generation enterprise SSDs? Are you a fast learner and enjoy synthesizing knowledge in to practice? Western Digital is a leader in the design of world class enterprise class SSD products. We are looking for a strong RTL Design Engineer to work on next generation enterprise SSD Development Platforms. The candidate must be a highly motivated self-starter who will thrive in this dynamic, cutting-edge environment. A fundamental part of our strategy is having desirable and powerful Development Platform that enable Engineering teams to deliver products at fast pace. Creating these platforms involves a close partnership between Hardware team, Firmware engineers, ASIC designers, and Program team. We are currently building the next generation and we need you!
You are responsible for providing technical knowhow in FPGA development, from design feasibility builds all the way to building debug images for resolving issues. You will be making RTL changes to map the design into FPGA system (Synthesis and place&route) and defining constraints for the FPGA builds. You will also be automating FPGA build flow to make it a push button build environment for other design engineers to be self serving build needs. Good understanding of STA is a must. You will also participate in documentation and defining FPGA implementation process for various stages of the FPGA development.
1.Understand controller architecture and propose design partitioning to fit within FPGA system's available resources
Defining streamlined FPGA build flow with nightly builds
2.Must be hands-on when it comes to RTL Coding, creating or customizing IP designs and simulation
3.Conduct and review different parts of the FPGA builds including tools log, utilization reports and timing reports
4.Ability to communicate effectively with other groups such as Architecture group, ASIC design, FPGA HW design group, Firmware team, program management.
5.Motivated and self-driven. A Team player is a must
6.Able to read hardware schematic design
7.Proficiency with Microsoft Office applications such as Word, Excel, and PowerPoint, Visio is required.
|工作待遇：||待遇面議 (經常性薪資達4萬元或以上) 薪資行情|
1. 彈性工時, 人性化管理
3. 勞保/健保完全依照法令規定投保, 依法並為個人提撥6%的勞退金
4. 完整且優渥的團保內容 (壽險/意外險/醫療住院險/癌症險) 配偶子女的團保全額由公司付費
臺灣分公司目前亟需ASIC chip lead, Firmware engineer, Design Verification 之人才, 非常歡迎您的加入. 公司位於台元科技園區, 不但軟硬體設備好,且跨國的工作環境更能開拓您工作視野與領域. 美式的工作環境與氣氛,正等待想要一展長才的您加入!
英文 -- 聽 /中等、說 /中等、讀 /中等、寫 /中等
Bachelor's/Master's degree in Electrical Engineering, Computer Engineering, or related technical degree is required.
Minimum 2-4 years’ experience with FPGA tools
Must have experience designing high density FPGAs, fundamental knowledge of FPGA internal architecture, FPGA IO Design, understanding device utilization and timing
Experience with RTL Simulation tools (Cadence Incisive), Synplify Premier, Identify debugger, Xilinx Vivado, Xilinx ILA, Synopsys Verdi, ARM ICE debuggers
Basic software development experience using C and/or Linux (Perl/Shell/Python scripting) is required
Experience working with FPGA development platforms is a definite plus
Practical experience in hardware debug - use of test equipment (Oscilloscope, Logic Analyzer, Chipscope etc.).
Basic software development experience using C and/or Linux (Perl/Shell scripting) is a plus