4/22 Staff/Sr. CPLD/FPGA Firmware Engineer (Server)
- 新北市五股區
- 4年以上
- 大學
The Staff/Sr. Engineer, CPLD will be based in Taiwan Taipei Wugu Site. The Staff/Sr. Engineer, CPLD performs the
The Staff/Sr. Engineer, CPLD will be based in Taiwan Taipei Wugu Site. The Staff/Sr. Engineer, CPLD performs the
1. Work closely with Hardware, BIOS ,BMC, and Firmware team for CPLD / FPGA design, validation, and maintenance. 2. Develop
【工作內容】 1. 數位電路邏輯控制程式設計 2. 基本通訊界面控制 (UART/I2C/SPGIO/SPI) 3. CPLD規格評估 4. CPLD規格書規劃、撰寫、維護 5. Verilog/VHDL模擬除錯設計 6. CPLD測試、除錯、驗
server products including FPGA/CPLD and MCU base designs. • Develop System Level Architectures for sub-system designs. • Build,
、網路資通安全、負載平衡、路由器、網路監控錄影主機 (NVR)、網路儲存伺服器(NAS)等。 【工作職責】 1. CPLD/FPGA design for X86 system. 2. Co-work with Hardware/Software
- 負責開發與設計相控陣列/光達/雷達硬體。 - 開發FPGA/CPLD 相關專案與Verilog/VHDL程式設計。 - 客製化高速 I2C, SPI, MIPI, UART, and Ethernet等IP。 - 進行FPGA/CPLD專案可
Responsibilities: 1.技術可行性分析 2.硬體線路設計 3.硬體設計審查和BOM產出 4.審查 PCB Layout 5.執行開機測試 和執行除錯 Work Location: ●新北市土城區自由街2號
1.Server CPLD設計開發、測試、除錯、驗證及最佳化 2.基本通訊界面控制(UART/I2C/SPGIO/SPI) 3.CPLD規格評估、規格書撰寫、維護 4.跨部門合作、分析解決問題
1. 主FPGA與CPLD專案開發與維護 2. 熟RTL coding, 具Xilinx ISE/Vivado或Altera Quartus II專案設計經驗 3. 能與軟,韌,硬體等相關部門co-work 4. 具Xilinx PCIe 與
plan writing 4. CPLD code design 5. BOM/material maintain 6. Product debugging/testing
1. 開發CPLD/FPGA/MCU等韌體,應用在網通、IoT等相關產業 2. 開發具有人工智慧的應用裝置 3. 有電路版設計經驗尤佳
1. 負責 FPGA 功能驗證、程式開發、測試、除錯及維護 2. 熟悉 FPGA: >> Familiar with Verilog RTL design. >> Familiar with RTL simulation, timing analysis using Xilinx Vivado Design Suite. >> Familiar with FGPA digital validation and test pattern generation using (system)ILA, logic analyzer, high-speed oscilloscope, etc. >> Familiar with Xilinx FPGA serdes IO, and selectIO. >> Familiar with Xilinx IP design and packaging. >> Familiar with at least one Xilinx FPGA device. >> Familiar with Xilinx HLS is a plus. >> Familiar with Xilinx Zynq SoC is a plus. 3. 熟悉 Xilinx、Altera FPGA 架構與設計 4. 熟悉 VHDL、Verilog、C、C++ 等 5. 具I2C、SPI通訊介面運作經驗者
單晶片.微處理器等之應用設計,包括單晶C語言,PIC,AVR...等任一語言,或FPGA,CPLD等之應用設計皆可.
1. Ethernet Switch hardware design, debug, evaluation, and verification 2. Responsible for PCB material selection (SI/PI considered), schematics design, PCB layout constraint & review, HW DVT test and 2nd source verification...etc. 3. Writing and maintaining the hardware specification of the projects, failure analysis report if needed 4. Study tools & instruments for design & validation
Spec/test plan documentation. 4. CPLD code design (Verilog)(VHDL) 5. BOM/material maintaining 6. Product debugging/testing/
1. Server硬體線路設計與layout design review 2. 板端電路驗證與分析,問題排除 3. 團隊合作開發設計、量測驗證、認證、問題協調及解決 4. 協助解決試產不良分析問題
with digital circuit & computer architecture. 4. Familiar with Altera or Lattice FPGA/CPLD design and development process
主要工作內容: 1. Explore/Develop New Technology 2. Circuit Design 3. Layout Design 4. Debug and Test 5. Create Test Plan and Test report 6. Proposal and H/W Spec design 7. Manage Project and Communication with Customer 次要工作內容: 1. Create BOM 2. Material prepare 3. Create Part number 4. Component sourcing **核薪與職稱將依據人選學經歷背景進行核敘**
Summary: • Responsible for motherboard/backplane CPLD coding based on requirement. • Familiar with X86 system and I2C, SPI