fixed-point algorithm and cost reduction algorithm developing. 4.Familiar with SystemC to RTL flow is plus.
algorithm for our upcoming WiFi products. Duties include but not limited to micro-architecture definition, RTL
1. RTL design of digital baseband modem 2. lab verification of phy algorithm such as FFT, Viterbi, etc. 3. area/power/
1.AI Accelerator architecture exploration 2.AI Accelerator RTL design & implementation 3.Chip integration
Computer Science. Skills/Experience 2.Good team player and communication skills. 3.Good Knowledge of RTL coding , Chip
(1)RTL coding for baseband design (2) FPGA implementation
and coverage collections • Regression setup and debug at RTL level and gate sim level working with design team
-About 艾盟仕- 國際品牌的營銷伙伴，給予多國在地品牌總代理（台灣、大陸、越南）銷售管理服務。 包括運動系列專業團隊- 快速成長的年輕團隊，邀你一同攜手開拓。 ★工作地點：面談確認後，依個人的居住地再分配門市 【角色定位/工作場景】 1.介紹及銷售商品/店鋪整潔維護/貨品帳務管理 2.商品諮詢與銷售 3.建立顧客關係與維護 4.店務與商品庫存管理 5.主管交付事項 【專業能力/產業歷練】 ＞具休閒或運動服飾銷售經驗，若具休閒服飾品牌銷售經驗者更佳。 ＞活潑外性，喜好與人接觸 ＞有數字觀念，擅長銷售管理 ＞對流行服飾趨勢瞭解，成為客戶穿搭諮詢伙伴 ＞願意挑戰業務數字，為自我帶來獎金報酬
Andes is a leading RISCV CPU IP company and Andes Deep Learning Accelerator (AnDLA) is our AI processor solution for efficient edge AI devices. AnDLA support most heavy computation load operation in deep learning inference phase. And the candidate is expected to design a AI behavior model from spec to implementation with the purpose of architecture exploration, DLA PPA optimization, and end-to-end application optimization co-work with Andes AI-SW/HW/tool team. =================== Responsibilities =================== 1. Build an deep learning hardware accelerator (DLA) model for architecture optimization. - Model lib compatible with Andes SW AI framework - Hardware profiling spec define and model realization 2. The behavior model can be integrated in hardware UVM system for hardware verification - Support both unit-test (UT) and integration-test (IT) - Flexible register / cmd parser for different HW implementation 3. Co-work with DLA HW/SW/Tool RD for end-to-end system optimization - HW: System spec and DLA architecture exploration - SW: Efficient and flexible API/lib design - Tool: AI deploy flow function specification
our team: 1. 3-10 years of working experience in Firmware development. 2. Familiar in Verilog RTL language. Experienced
maintaining, documenting, and supporting existing system level memory model products. Perform as individual contributor for RTL
開發和相關測試 具備條件: - 具3年以上Digital IC design或FPGA開發相關經驗 - 熟悉RTL coding、simulation & synthesis流程及其開發工具使用 - 具C/C++ coding 和 debug 能
1. 負責 FPGA 功能驗證、程式開發、測試、除錯及維護 2. 熟悉 FPGA: >> Familiar with Verilog RTL design. >> Familiar with RTL simulation, timing
1. Digital circuit design and verification 2. Familiar with ASIC design flow, synthesis, and related tools 3. FPGA development and verification
工作技能：撰寫硬體語言程式、數位晶片產品開發、數位電路分析設計、數位電路驗證、FPGA。 擅長工具：Verilog、C、Python、Perl、TCL、EDA、FPGA、RTL、EDA tool: NC-Verilog、Synopsys DC、
1. ASIC開發數位電路設計,協助客戶制定規格並提供技術協助 2. SoC硬體整合及驗證環境之研發與客戶服務 3.具專案管理能力
1. 根據客戶需求及產品的規格提供客製化電路、數位IP設計。 2. 需熟悉Verilog RTL coding。 3. 負責 IP Verification。 4. 具獨立處理問題能力，必要時支援on-site support。
LCD/AMOLED相關IP設計 (CABC/SPR/DSC/Scaler或其他IP) 【需求條件】 1.數位電路設計相關設計經驗5年以上 2.熟悉Verilog RTL/STA分析與設計流程 3.對於新技術有強烈學習意願