1. FPGA 相關專案開發 2. 基於Xilinx RFSoC嵌入式系統開發 3. 負責低軌衛星地面接收站開發 4. 負責衛星通訊酬載開發 5. 協同團隊整合優化產品
understanding of Design for Testing including Scan/ATPG/BIST/JTAG -Familiar with Verilog -Experiences with RTL and Simulation.
for the stage from RTL frozen to tape out, include synthesis, formal verification, constraints definition, timing closure/sign
體經驗尤佳 ※具備1-2年直接經驗尤佳 ※具備以下工具經驗尤佳： Linux Windows 10 C# C++ AutoCAD Cadence Allegro Circuit Design DSP Firmware RTL Verilog
1. 根據客戶需求及產品的規格提供客製化電路、數位IP設計。 2. 需熟悉Verilog RTL coding。 3. 負責 IP Verification。 4. 具獨立處理問題能力，必要時支援on-site support。
1．能獨立面對客戶,了解客戶需求,提供專業建議,規劃解決方案. 2．編寫技術文件 3．熟VHDL或Verilog硬體描述語言, 懂基礎C/C++,基礎Linux. 4．一年以上FPGA使用經驗(Xilinx佳) 5．強烈徵求嵌入式FPGA人才(Embedded FPGA) (eFPGA)
1.Complete the front-end design tasks from RTL design to netlist 2.Main jobs contains spec study, architecture plan, RTL
Summary : Artilux are looking for an outstanding engineer who is excited to bring new architectures for advanced ICs, with high quality and exceptional performance. Roles & Responsibilities： • Design, simulate, and verify the design of digital blocks/systems • Familiar with digital IC design back-end flow • Handle and complete assigned projects independently • Skillful communication with cross-functional members, and attending the technical meeting
# Job Overview - Our team is maintaining a trading system for general clients and developing a low-latency trading system for professional clients. As time progresses, these initial systems require updates and enhancements, and we need a robust team to build the next generation of systems. At the early stage of team expansion, we are seeking three exceptional senior C++ engineers: 1. C++ Language Expert 2. C++ System Programming and Optimization Engineer 3. Senior Vitis FPGA HLS C++ Engineer (this position) - In our company, there are no restrictive network policies or bureaucratic procedures that slow down development, except for stringent cybersecurity regulations when collaborating with financial institutions on deployment environments. Daily development is unrestricted, allowing the use of modern tools for efficient development. # Main Responsibilities - You don't have to be a C++ language expert, but you should possess enough Modern C++ development experience and knowledge to avoid language-level errors leading to program crashes, incorrect results, or poor performance. Your code will be reviewed by C++ experts who will provide advice and from whom you can learn to avoid writing performance-degrading C++ code. - The primary task is to implement parts of the trading system on the FPGA network card of the Xilinx Alveo Platform, focusing on optimizing FPGA programming to achieve sub-microsecond latency in our trading system. - Participate in architectural discussions, segment the trading system, and prioritize the implementation of the most critical parts on FPGA for optimization. # Required Skills - A Master's degree or higher in Electrical Engineering, Electronic Engineering or Computer Science from domestic or international institutions. - Advanced Linux system operation skills, knowledge of using CMake and GNU make, familiar with command-line editors like vim and NeoVim in Linux. - Proficiency in Vitis IDE, Vitis HLS graphical development interface, and performance analysis tools. - Mastery of XRT library and HLS Vitis Libraries. - Understanding of which C++ mechanisms and library components can be used in PL kernel development. - Familiarity with using v++, vitis_hls, writing related TCL scripts and v++ config files, and integrating the build process into CMakeLists.txt. - Knowledge of handling TCP and UDP network packets on the Xilinx Alveo Platform. - Experience in designing test benches to validate designs. - Advanced operations in Git command line. - Advanced English reading skills. - Utilization of modern AI tools to enhance work and learning efficiency, facing various unknown challenges.
熟悉FPGA應用及相關程式撰寫，或曾使用過FPGA有興趣更深入研究者皆歡迎來電洽談。
flow design Qualifications/Skills: - Familiarity with RTL coding and verification - Familiarity with scripting (such as TCL
relevant state-of-the-arts 3. Experienced in RTL design, IP integration, FPGA verification, or SW/HW co-simulation 4.Pay
1. ARM / RISC-V CPU 相關電路設計 2. MCU週邊 SPI / I2C / UART 相關電路設計 3. RTL to Xilinx FPGA 設計 4. DV / UVM / DFT 相關經驗
micro-architecture definition, RTL design, RTL and model co-simulation, regressions, and respective debugging activities •
& consumer products. Job Responsibilities - Write RTL models in Verilog for the different flavors of IOs. - Build
1.USB4/USB3/DP/HDMI/PCIe IPs, and Whole Chip Verification 2.Familiar with System Verilog and UVM 3.Capable of setting up the testbench for different purpose and scope (IP, Partition, or whole chip) 4.Develop verification plan for improving coverage holes on each IP 5.Develop Bus Functional Model (BFM), assertions, and cover groups to verify in- house interface/design
-About 艾盟仕- 國際品牌的營銷伙伴，給予多國在地品牌總代理（台灣、大陸、越南）銷售管理服務。 包括運動系列專業團隊- 快速成長的年輕團隊，邀你一同攜手開拓。 ★工作地點：面談確認後，依個人的居住地再分配門市 【角色定位/工作場景】 1.介紹及銷售商品/店鋪整潔維護/貨品帳務管理 2.商品諮詢與銷售 3.建立顧客關係與維護 4.店務與商品庫存管理 5.主管交付事項 【專業能力/產業歷練】 ＞具休閒或運動服飾銷售經驗，若具休閒服飾品牌銷售經驗者更佳。 ＞活潑外性，喜好與人接觸 ＞有數字觀念，擅長銷售管理 ＞對流行服飾趨勢瞭解，成為客戶穿搭諮詢伙伴 ＞願意挑戰業務數字，為自我帶來獎金報酬
1. M.S/Ph.D in EE/ECE degrees with specialization in fields related to wireless signal processing. 2. Solid understanding of wireless communication theory and PHY signal processing (MIMO/OFDM, beamforming, timing/frequency acquisition, AGC, channel estimation, signal design, multiuser, indoor locating, wireless sensing, …etc.) 3. Experience in using C/C++/Python/MATLAB for modeling/simulations of wireless links. 4. Knowledge of current cellular communication standards: 5G (NR) and 4G (LTE). 5. Familiar with 3GPP 5G RAN architecture, O-RAN specifications. Also, RLC/MAC layer and different types of control a plus.
1. Ethernet SerDes高速介面數位設計 (USXGMII, 25G Base-R) 2. 依據系統規格, 執行架構設計以及撰寫硬體描述語言 (RTL), 和軟體同仁合作進行相關驗證 3. 具有高速介面或 high level