數位IC設計工程師
- 台北市信義區
- 經歷不拘
- 碩士
1. Architecture design, RTL coding, simulation, synthesis, LEC, STA 2. Digital front-end design flow
1. Architecture design, RTL coding, simulation, synthesis, LEC, STA 2. Digital front-end design flow
deploy the synthesis solutions to help customers successful with their design requirements - Be responsible for product
1. 負責MCU/DSP開發 2. Embedded/SoC chip integration(floorplan design, package bonding, whole chip synthesis) 3. FPGA
(1) Ongoing project R2G synthesis (top down/button up) (2) Logic equivalent check with R2G/G2G (3) Pre netlist timing
Physical design, including floorplan, power plan, physical synthesis, clock tree synthesis, routing, DRC/LVS to tapeout.
1. Support oncology drug discovery programs through design and synthesis of potential drugs. 2. Design and synthesize
driving and optimizing synthesis, implementing DFT circuits, power optimization, static timing analysis, and design
tree synthesis, timing sign off and physical verification. 2. For DFT engineers, need to able to implement scan chain, atpg,
implementation & integration. • Set up RTL, Lint, Synthesis reviews & design quality processes. • Establish & review
development, solid-phase synthesis, purification, and downstream processing of chemically modified oligonucleotides and
1. ARM CPU/GPU, DSP front end implementation including high speed RTL synthesis and DFT. 2. Front end verification
coding, simulation, debugging, Lint, CDC, synthesis, LEC, SDC, and STA 3.Support other functional teams (such as IP ,DFT , and
成晶片驗證並T/O 【需求條件】 1. 碩士畢業,數位IC設計3年以上經驗 2. 熟悉ASIC設計和開發流程 3. 熟悉Verilog, Synthesis, formal, STA, FPGA驗證等流程 4. 熟悉上層整合和IP介面 5. 具有
Perform synthesis and timing analysis to ensure the chip meets performance criteria. - Work closely with back-end engineers for
generation, mixed signal, wireless products. The role will focus on the areas of RTL design, FPGA synthesis and FPGA system
(1) Responsible for rtl2gds design flow development (2) Build, debug, maintain project working environments (3) In house EDA utility development (4) Deploy tracking metrics and interactive dashboard for project status review
synthesis實作經驗或FPGA實作經驗者尤佳
● Design and synthesize linkers and payloads for protein-drug conjugates development ● Development of scale-up process ● Large-scale purification of nature product
synthesis and routing. · Support STA timing analysis and fixing. · Perform physical verification, including DRC, LVS, IR drop
compatible for rapid access to small molecule targets (strong organic synthesis background is required) 2. Learn and employ
Modern analog building blocks in advanced CMOS technologies need digital to improve their performance. As Analog-Mixed Signal Verification Engineer, you will be responsible for implementing the top-level verification in an analog-digital design world. 1. Set up the tool flow for top-level verification in analog-on-top, mixed-signal or digital-on-top environments. 2. Support production level testing and verification for preproduction, qualification and production. 3. As a senior design engineer, you will mentor team member in design concept and best practices.