This is a Verilog modeling and characterization engineer position in Methodology, Flow and Design Kit team involved in
Signal Verification solution development typically needs to work with experts from different areas (Verilog simulator, SPICE
雷達數位IC FPGA Prototyping 硬體部門合作 FPGA daughter board 演算法部門合作撰寫 Verilog 韌體部門合作驗證 FPGA
- 負責開發與設計相控陣列/光達/雷達硬體。 - 開發FPGA/CPLD 相關專案與Verilog/VHDL程式設計。 - 客製化高速 I2C, SPI, MIPI, UART, and Ethernet等IP。 - 進行FPGA/CPLD專案可
【邀請您將104履歷同步上傳至華邦官方網站，將使您的履歷優先被主管看見】 此職缺履歷登錄網址：https://bit.ly/3VbIz0v 1. DRAM Verilog /VCS/Modelsim behavior models
layer. 3、Study related specification. 4、Develop in verilog language. 5、Use Matlab for verification. 6、Use Xilinx Vitis tool
• Co-work with hardware designers to verify designs with system verilog and system verilog assertion. • Building,
JMicron, founded in 2001 and located in Hsinchu Science Park, is a leading provider for high speed SerDes bridge controller SOC's mainly in storage application utilizing USB, PCIe, and SATA. With recent merger of KaiKuTek, our product portfolio now extends to 3D mmWave smart sensor for gesture recognition and AIoT markets. We now possess key technologies in areas such as Antenna-in-Package (AiP), ML algorithm, AI accelerator, as well as 60 GHz radar transceiver design. This new sensing technology will change and redefine human-machine interface as we know today, and mmWave technology combined with high speed SerDes will open door to many new possibilities and application frontiers. JMicron is looking for enthusiastic digital IC design engineers willing to take upon new challenges of working closely with cross functional teams, including analog/RFIC designers, hardware engineers, software and firmware engineers, production and testing as well as marketing and FAE, to optimize the overall SoC performance in terms of power, area, functionality, testability as well as to create proof-of-concept for new customer engagement.
programming skills in languages like Verilog and possibly high-level languages like C/C++. Experience in AI/ML: In-depth
【工作內容】 1. IP介面控制和時序處理 2. 晶片上層連線和系統整合 3. 使用Verilog設計和功能模擬 4. 使用FPGA進行功能驗證 5. 晶片合成並完成DFT, multi-clock和timing等設計 6. 與後段整合合作, 完
Digital design verification using UVM and System Verilog.
languages (Verilog, SysVerilog, UVM), strong documentation skills for spec/test plan documents • Exposure/Basic comprehension of
1. 具有類比IC設計經驗或相關科系/所畢業 2. Familiar with High-Speed Transceiver Designs, CDR/PLL, ADC/DAC, Delta-Sigma Modultors, DC-DC Converters, or Linear Regulators. 3. USB, DP, HDMI, PCIe or SATA experience is a plus.
職務說明 1.3+ years experiences in ASIC/SOC IC design, sample verification 2.Experience on RTL / Verilog design, synthesize,
1. 負責 FPGA 功能驗證、程式開發、測試、除錯及維護 2. 熟悉 FPGA: >> Familiar with Verilog RTL design. >> Familiar with RTL simulation, timing
1.In charge of digital circuit design/verify by Verilog 2.Implement FPGA development & architecture. 3.Familiar with Xilinx
1. ASIC開發數位電路設計,協助客戶制定規格並提供技術協助 2. SoC硬體整合及驗證環境之研發與客戶服務 3.具專案管理能力
1．能獨立面對客戶,了解客戶需求,提供專業建議,規劃解決方案. 2．編寫技術文件 3．熟VHDL或Verilog硬體描述語言, 懂基礎C/C++,基礎Linux. 4．一年以上FPGA使用經驗(Xilinx佳) 5．強烈徵求嵌入式FPGA
1. 數位IC電路設計、模擬與驗證 2. 主管交辦事項
Account for pipeline stages, data dependencies, and timing constraints. • Use tools like Verilog, system-Verilog, or specialized