4/22 NPU AI晶片系統架構開發資深工程師
- Inventec_英業達股份有限公司
- 電腦及其週邊設備製造業
- 台北市士林區
- 經歷不拘
- 碩士
英業達近年進攻各種邊緣 AI 運算應用領域,我們是英業達 AI 晶片設計研發團隊,具備多年 AI 與 Processor IC 設計經驗,現正積極投入類神經網路加速器 IP 研發,我們主要工作為應用 Verilog 與 Python,導入來自國際
英業達近年進攻各種邊緣 AI 運算應用領域,我們是英業達 AI 晶片設計研發團隊,具備多年 AI 與 Processor IC 設計經驗,現正積極投入類神經網路加速器 IP 研發,我們主要工作為應用 Verilog 與 Python,導入來自國際
1. 負責 FPGA 功能驗證、程式開發、測試、除錯及維護 2. 熟悉 FPGA: >> Familiar with Verilog RTL design. >> Familiar with RTL simulation, timing
team to debug and find out the root cause. 3. RTL coding by Verilog or VHDL, writing CPLD design spec document and design
Responsibilities 1. Develop for automation in Unix/Linux environment (1) Python, TCL, shell script, perl 2. Develop, maintain and enhance ASIC design infrastructure (1) Version control, testing automation, … (2) EDA Tool maintenance and license management 3. Work with EDA vendors to (1) Evaluate new tools and flow (2) track and resolve tool issues 4. Install, configure and support foundry PDK
1. Develop and maintain block and chip level verification environment 2. Execute and manage test plan 3. In charge of Subsystem DV for SPEC-IN Project 1.block 與 chip level 驗證環境開發與維護 2.規劃與執行測試項目 3.依據規格負責子系統驗證 The working place is Hsinchu, the United States and Canada
1. cortex-M3 應用與程式開發經驗. 2. 熟悉C語言或Verilog 語言. 3. USB應用或程式開發. 4. 有燒錄器或ICE開發經驗. 5. 有BCB or VC++ or C# 經驗者佳.
1. 數位IC電路設計、模擬與驗證 2. 主管交辦事項
Develop and maintain environment for SOC pre-silicon verification of: • RTL and netlist simulation • CRV for system fabric • Power-aware simulation • Formal CC and FPV • System level verification with SVA
1. 熟Verilog及C/C++語言設計。 2. 規劃執行產品韌體之撰寫。 3. 執行、協助或配合韌體新技術之研發、導入。 4. 執行產品韌體測試。
1. 具有類比IC設計經驗或相關科系/所畢業 2. Familiar with High-Speed Transceiver Designs, CDR/PLL, ADC/DAC, Delta-Sigma Modultors, DC-DC Converters, or Linear Regulators. 3. USB, DP, HDMI, PCIe or SATA experience is a plus.
1. 熟悉Verilog HDL coding & simulation 2. 具馬達驅動控制相關經驗者佳,數位/混合信號IC設計相關經驗(論文或專題相關)
1. 熟悉Verilog與FPGA環境與操作,能開發prototype。 2. 具備USB/PD/DP/HDMI等protocol設計相關。 3. 有高速介面設計經驗佳。 4. 具備Synthesis, STA, Formal
Unix shell languages; understanding of issues and modeling of variation in deep sub-micron technologies; knowledge of verilog
1. ASIC開發數位電路設計,協助客戶制定規格並提供技術協助 2. SoC硬體整合及驗證環境之研發與客戶服務 3.具專案管理能力
languages Verilog/SystemVerilog is required along with experience using RTL verification tools and flows. Debugging experience.
1. Develop integrated verification environment. 2. Verify designs with system verilog and system verilog assertion. 3.
Product : OLED DDI 1. Develop integrated verification environment. 2. Verify designs with system verilog and system
The Role: As a Design Verification Engineer, you will work with CPU designers, compiler team, performance team, and system verification team to generate the test cases automatically to fit those teams verification requirements in different perspectives. Your responsibilities will target establishing a highly scalable and reusable constrained random test bench that produces coverage driven tests. Responsibilities: - Review and influence product definition and specifications from a verification perspective and collaborate closely with the design team on feature specifications, test plans, and failure analysis. - Develop checkers and assertions to verify the memory subsystem designs with interconnect. - Develop tools, test benches, and test suites (UVM, C++/C, or otherwise as needed) to execute test plans. - Develop and maintain an in-house Verification IP (VIP) tailored for memory subsystem and interconnect testing - Write functional coverage, analyze both code and functional coverage, and close coverage holes.
1.數位邏輯設計並熟悉RTL Coding架構。 2.熟悉 Xilinx、Altera FPGA 架構與設計。 3.研發設計網通應用IP。 4.協助開發與驗證FPGA電路(Schematic)。