You will perform Signal Integrity analysis, collaborating with different engineering teams to balance system/product constraints with high speed signals.
【Job Description】
• Perform pre-layout and post-layout simulation flow.
• Create simulation models and develop simulation methodology for SI/PI design.
• Stackup review and layer assignment for High speed and PDN
• Use simulation and lab data to support design troubleshooting and propose corrective actions, drive failure analysis, root cause efforts, and design of experiments to resolve problems.
• Analyze package/PCB PDNs and make design trade-off and negotiate power budgets.
• Explore various design elements including different modules, memories, low/high speed buses, cables, components, their physics of operation, and impacts on system performance.
• Provide system SI design guidance and perform post-layout review and optimization.
• Work closely with EE design team and PCB layout team to optimize SI design based on the simulation data.
• Generate simulation report based on the data with clear SI recommendation.
【Minimum Qualifications】
• Must have an MS or PhD in Electrical Engineering or Electrical and Computer Engineering
• Proved experiences on board level signal and power integrity.
• Board-level system architecture, I/O structures & topologies
• Printed Circuit Board (PCB) design and layout process and methodology
• Experience with signal integrity modeling tools, including 3D EM modeling (Ansys HFSS) and simulation (Agilent ADS or similar) software
• Experience with signal and power integrity analysis tools (ex: HSPICE, Sigrity tools, etc)
• Lab hands on experiences on TDR, VNA, BERTscope, digital scopes